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Core8051
Table 5 ? Core8051 Pin Description (Continued)
Name
Type
Polarity/Bus Size Description
membank
BreakIn
Input
Input
4
High
Optional code memory bank selection. If not used, connect to logic 0 values.
Break bus input. When sampled high, a breakpoint is generated. If not used,
connect to logic 0.
BreakOut
Output
High
Break bus output. This will be driven high when Core8051 stops emulation. This
can be connected to an open-drain Break bus that connects to multiple
processors, so that when any CPU stops, all others on the bus are stopped
within a few clock cycles.
TrigOut
Output
High
Trigger output. This signal can be optionally connected to external test
equipment to cross-trigger with internal Core8051 activity.
AuxOut
Output
High
Auxiliary output. This signal is an optional general-purpose output that can be
controlled via the OCI debugger software.
TraceA
Output
8
Trace address outputs. This bus should be connected to external RAM address
pins for trace debug memory.
TraceDI
Output
20
Trace data to external synchronous RAM data input pins for trace debug
memory.
TraceDO
Input
20
Trace data from external synchronous RAM data output pins for trace debug
memory. If OCI is not used, connect to logic 0 values.
TraceWr
Output
High
Trace write signal to external synchronous RAM write enable for trace debug
memory.
External Interrupt Inputs
int0
int1
int0a
int1a
int2
int3
int4
int5
int6
int7
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Low/Fall
Low/Fall
High
High
High
High
High
High
High
High
External interrupt 0
External interrupt 1
External interrupt 0a
External interrupt 1a
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
Serial Port Interface
rxdi
rxdo
txd
Input
Output
Output
–
–
–
Serial port receive data
Serial port transmit data in mode 0
Serial port transmit data or data clock in mode 0
Timer Inputs
t0
t1
Input
Input
Fall
Fall
Timer 0 external input
Timer 1 external input
External Memory Interface
mempsacki
Input
High
Program memory read acknowledge
v6.0
7
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